02 Gates

Gates¶

a	b	a'	\(a \cdot b\)	a + b	a nand b	a nor b	a xor b	a xnor b
0	0	1	0	0	1	1	0	1
0	1		0	1	1	0	1	0
1	0	0	0	1	1	0	1	0
1	1		1	1	0	0	0	1

Verilog Codes¶

module gates(y, a, b);
  input a, b;
  output y;
  wire andg, org, notg, nandg, norg, xorg, xnorg;

  assign andg = a & b;
  assign org = a | b;
  assign notg = ~a;

  assign nandg = ~ (a&b);
  assign norg = ~ (a|b);

  assign xorg = a^b;
  assign xnorg = ~(a^b);

endmodule

Bubbled Gates¶

inputs to the gates are negated

	Bubbled AND	Bubbled OR
Function	\(y = a' \cdot b'\)	\(y = a' + b'\)
Another name	Negative AND	Negative OR
equivalent to	NOR	NAND

Verilog¶

module gates(y, a, b);
  input a, b;
  output y;
  wire band, bor;

  assign band = ~a & ~b;
  assign bor = ~a | ~b;

endmodule

Universal Gates¶

NAND & NOR are called universal gates because we can implement all other gates with just these 2

for NOT¶

for NAND and OR, just split a single input into 2 wires and pass it through the gate

module gates(y, z, a, b);
  input a, b;
  output y, z;

  assign y = nand(a, b);
  assign z = nor(a, b);

endmodule

for OR¶

NOR

use a gate
complement the output

NAND

complement a, b individually
Complement the output using another gate

module gates(y, a, b);
  input a, b;
  output y;
  wire p, q;

  assign p = nor(a, b); // (a+b)'
  assign y = nor(p, p); // a+b

  assign p = nand(a, a); // a'
  assign q = nand(b, b); // b'
  assign y = nand(p, q); // (a' . b')' = a + b

endmodule

for AND¶