12 FlipFlops

Flip Flops¶

flip fl==o==p; cl==o==ck

in latches with enabled, it is observed that inputs are recognized only when enabled is 1. Therefore, it is possible to replace enabled with a momentary pulse called clock so that the inputs can be recognized only for a specified time. Such a device is called a flipflop.

(c means clock)

FF are usually edge triggered

the below truth tables are for positive trigger

SR Flip Flop¶

almost identical compared to SR Latch, just that there is a clock

Expression¶

\(Q_{n+1} = S + R' Q_n\) (simplified using KMap)

D-Flip Flop¶

also called as transparent flip flop

Expression¶

\(Q_{n+1} = d\) (simplified using KMap)

JK Flip Flop¶

SR replaced with JK

Output of

• \(Q'\) will be another input of first NAND gate
• \(Q\) will be another input of second NAND gate

\(Q_{n+1} = j Q'_n + k' Q_n\)

T Flip Flop¶

Toggle Flip Flop

similar to XOR gate

We only want 00 and 11

Remove J and K, add T

\(Q_{n+1} = T \oplus Qn\)

FF with Preset and Reset/clear¶

Active High¶

Active Low¶

Diagrams¶

Verilog¶

module srff(q,qbar, s, r, c);
  input s, r, c;
  output q, qbar;
  wire nand1, nand2;

  nand(nand1, s, c);
  nand(nand2, r, c);

  nand(q, nand1, qbar);
  nand(qbar, nand2, q);
endmodule

module testbench;
  reg s, r, c; // reg means storage
  wire q, qbar;

  initial begin
    c = 1'b1;
    repeat(2) #200 c = ~c;
  end

  initial begin
    s = 1'b0;
    repeat(8) #25 s = ~s;
  end

  initial begin
    r = 1'b1;
    repeat(13) #15 r = ~r;
  end
endmodule

Dlatch using

Blocking¶

module dLatch(input d, c, output reg q, qbar);
  always @ (d, c);
    if(c) begin
      #4 q = d;
      #4 qbar = ~d;
    end
endmodule

Non-Blocking¶

Timing Diagram¶

basically the graph thingy

you’ll do it obviously

Excitation Table¶

one FF var will be reverse of the other helpful for JK and SR

helps us to perform flip-flop conversions

In regular truth tables, (j,k, Qn) are inputs and Qn+1 is output in excitation table, Qn and Qn+1 are inputs and j and k are outputs

JK FF¶

T FF¶

similar to XOR gate

D FF¶

SR FF¶

Conversion¶

1. Identify source and destination FF
2. Tables
3. Draw Truth table for destination FF
4. extend it (change X into 0 and 1)
5. Draw excitation table of source FF
6. Merge both the tables
7. Draw KMap which provides expression for conversion with
8. inputs as
   1. source FF input vars
   2. \(Q_n\)
9. output as dest FF input vars
10. Draw circuit according to KMap

SR using D¶

\(S = D, R = D'\)

SR using JK¶

\(S = j Q'_n, R = k Q_n\)

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