15 Counters

Counter¶

is a register that goes through a prescribed sequence of states, upon the application of clock pulse

mod of a counter = no of states

Features

1. active low clock
2. active low reset
3. FF: JK/T

Binary Counter¶

follows a binary counting sequence (normal without any zigzag)

\(mod(N)\) counter that divides input frequency by \(n\) is called as ‘divided-by-\(n\)’ counter

Types¶

Counting method¶

1. up-counter \((0 \to n)\)
2. down-counter \((n \to 0)\)

Types¶

2-bit ripple w/ neg trigger¶

ripple means asynchoronous

storeable values \(= 0, 1, 2, 3\)

\(c_1 = Q_0\)

upcounter¶

down counter¶

When m = 0, the circuit acts as an upcounter; m = 1 down counter??????????

flowchart

subgraph Up
    p[00] --> q[01] --> r[10] --> s[11] --> p
end

subgraph Down
    a[00] -->    d[11] -->    c[10] --> b[01] --> a
end

IDK¶

For 2^nd FF¶

4-bit ripple w/ neg trigger¶

upcounter¶

BCD Ripple Counter¶

also called as decade

requires

• 4 FF
• NAND gate
• OR gate

4 decade counter¶

also called as 4 digit BCD counter

mod 10 counter

contains four BCD counters

Custom mod counters¶

not all states are used

1. Find no of FF the required no of FF is the smallest \(n\) that satisfies \(N \le 2^n\), where
   • \(N =\) no of states
   • \(n =\) no of FF
2. Write the counting sequence of the counter
3. Draw the truth table
4. If necessary, find the minimal expression for reset condition, using KMAP

Design of mod6 asynchoronous counter¶

Cascading of Ripple Counter¶

If we have 2 counters mod M and mod N, then the resulting cascaded ripple counter will be mod(MxN)

The MSB of the first(left) counter is connected to the clock of the second (right) counter

Synchoronous Counter¶

Design¶

1. identify the no of FF

2. counting sequence and state diagram

3. choice of FF, excitation table

4. minimal expression for excitation (KMAP)

5. kmap is drawn for J,K or T wrt the corresponding Present state variables

6. Logic Diagram

3 Bit upcounter¶

3 Bit downcounter¶

up/down¶

flowchart LR

000 --> |1|001
001 --> |0|000

• \(m = 0 \to\) downcounter
• \(m=1 \to\) upcounter

4 variable KMAP

BCD upcounter¶

10-15 are unused states

Special Conditions¶

Lockout/Deadlock¶

Both PS and NS are unused states

Self-Start¶

When a system is switched on and enters an unused state, and then after a few clock pulses, the system enters a used state

Steps¶

1. Fill up unused state as present state
2. Fill up FF i/p based on the equation obtained from KMAP
3. Fill up the next state (using excitation wrt present state and FF ip)

Question¶

Does design of a synchoronous BCD counter using JK FF have lockout condition?

unused states = {10, 11, 12, 13, 14, 15}

= {1010, 1011, 1100, 1101, 1110, 1111}

flowchart LR

subgraph Used
    0 --> 1 --> 2 --> 3 --> 4 --> 5 --> 6 --> 7 --> 8 --> 9 --> 0
end

subgraph Unused
    10 --> 11 --> 4
    12 --> 13 --> 6
    14 --> 15 --> 0
end

From unused state, the counter goes to used state after a few clock pulses and counts in a normal way

Hence, it is self-starting

Mod 6 counter¶

flowchart LR
000 --> 001 --> 010 --> 011 --> 100 --> 101 --> 000

unused states will be represented as don’t care in the KMAP

Self-start

Design a type D counter that goes through the states \(0, 1, 2, 4, 0, \dots\) , such that the unused states must always go to 0 on the own next clock pulse

flowchart LR
subgraph Used
    0 --> 1 --> 2 --> 4 --> 0
end
subgraph Unused
    3 & 5 & 6 & 7 --> 0
end

because of the given next states for the unused states, we cannot write it as don’t care for them

Using a JK counter, count \(3, 4, 6, 7, 3, \dots\)

Is Johnson counter lockout or self-start?

Lockout condition

Diagrams¶

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